Bist IP

The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing.
The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility.

The AI and HPC industries are advancing toward chiplet-based designs to achieve superior performance, as traditional monolithic SoCs face scaling challenges
Heterogeneous integration is driving semiconductor innovation but adds complexity to chip design, requiring advanced testing methodologies and improved Automated Test Equipment (ATE)
Increasing test patterns and limited package pins demand high-bandwidth IOs, while advancements in ATE capabilities further necessitate optimized GPIOs to support higher-speed, efficient and low-cost testing
Synopsys High-Speed Test IO IP is a cutting-edge IO interface solution that enables efficient, high-speed testing of complex semiconductor designs while minimizing hardware complexity and cost

The UniIC GDDR6 PHY，subsequently referred to as the UNIIC_GD6PHY, is designed for performance and power efficiency, its target is to deliver industry-leading data rates of up to 12Gbps/13Gbps/14Gbps and is compatible with JEDEC standard JEDEC250 and DFI 3.1
The UNIIC_GD6PHY is used to transfer the Command/Address and Datas between the memory controller and the GDDR6 DRAM device; _x000D_ The UNIIC_GD6PHY is available in Global Foundries FinFET 12LPP technology
The UNIIC_GD6PHY is fully documented and comes with a comprehensive set of deliverables for ease of system modeling and integration.

The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.
The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls.

This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.

Fully compliant with UHSII specification Ver. 4.x
Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
Supports data rates from 390Mbps to 1.56Gbps/ch
RCLK frequency: 26 to 56MHz
Built-in PLL and clock recovery

This DDR3/4 IP combo solution presented, is meticulously designed for high performance and low power consumption, utilizing sophisticated architecture and advanced technology.
Fabricated in TSMC’s 12nm CMOS process, this solution includes both controller and PHY IPs, providing comprehensive support for DDR3 and DDR4 memory interfaces.