HBM4E PHY and controller

Overview

Providing a Complete Solution for HBM4

The Cadence High-Bandwidth Memory generation 4 (HBM4E) PHY is optimized for systems that require the highest-bandwidth, low-latency memory solution. The memory subsystem consisting of PHY and controller supports data rates up to 12.8Gbps per data pin, featuring 32 independent channels, for a total data width of 2048 bits. The PHY is designed for a 2.5D system with a silicon interposer to route signals between the 3D DRAM stack and PHY. 

The fourth-generation design is optimized for low power consumption and low PHY area. Cadence provides the complete solution including PHY, controller, interposer, and package.

Key Features

  • Advanced clocking architecture minimizes clock jitter
  • DFI PHY Independent Mode for initialization and training
  • IEEE 1500 interface, memory BIST feature, and loop-back function
  • Supports lane repair
  • Designed for optimized interposer routing

Benefits

  • Highest Performance: HBM4E up to 12.8Gbps per pin
  • Low Latency: For data-intensive applications
  • Low Power and Area: Low-power control and advanced low-power modes with power down
  • Complete HBM Solution: Full system design including PHY, controller, interposer, and package
  • Easy integration: PHY is hardened and timing closed, including all I/O and decoupling capacitors
  • Excellent Support: Access to Cadence expert SI/PI team to support customer designs

Block Diagram

HBM4E PHY and controller Block Diagram

Technical Specifications

Short description
HBM4E PHY and controller
Vendor
Vendor Name
×
Semiconductor IP