Implement all recommendation test items for hight test coverage
The BIST can realize all eFlash testing items, covering UMC’s 40nm and 55nm processes, as well as SST’s 0.11um and 0.18um processes, and customized embedded eFlash IP wafer software testing and final testing. The BIST features a flexible serial interface, reducing the need for IC test pins and increasing testing flexibility. All testing functions can be individually activated or deactivated, and it provides a diagnostic mode to test memory defect addresses. Additionally, iSTART-TEK’s BISR can record the addresses of eFlash faults and use redundancy features to replace faulty eFlash, thereby improving the yield of eFlash chip products.
Interface
- JTAG
- IEEE 1149.7
- SPI