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AI Co-Processor IP

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Search (12)
Compare 12 IP from 5 vendors (1 - 10)
  • Vision AI DSP
    • Ceva-SensPro is a family of DSP cores architected to combine vision, Radar, and AI processing in a single architecture.
    • The silicon-proven cores provide scalable performance to cover a wide range of applications that combine vision processing, Radar/LiDAR processing, and AI inferencing to interpret their surroundings. These include automotive, robotics, surveillance, AR/VR, mobile devices, and smart homes.
    Block Diagram -- Vision AI DSP
  • LPDDR5X Secondary/Slave (memory side!) PHY
    • JEDEC standard LPDDR5X @ 8533Mbps (Mbits per second per pin)
    • Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
    • Support for byte-mode DRAM devices for high capacity systems
    • ZQ Calibration
  • LPDDR5 Secondary/Slave (memory side!) PHY
    • JEDEC standard LPDDR5 @ 6400 Mb per second per pin.
    • Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
    • Support for byte-mode DRAM devices for high capacity systems
    • ZQ Calibration
  • LPDDR4x Secondary/Slave (memory side!) PHY
    • JEDEC standard LPDDR4X @ 4267 Mb per second per pin.
    • Flexible channel architecture
  • LPDDR4x/5 Secondary/Slave (memory side!) PHY
    • Supports JEDEC standard LPDDR5, LPDDR4X, LPDDR4
    • Secondary side PHY
    • Custom implementations available
  • Audio and control DSP
    • Quad 16x16 MACs
    • Dual 32x32 MACs
    • 4-way VLIW
    Block Diagram -- Audio and control DSP
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
    • AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
    • It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
  • Neuromorphic Processor IP (Second Generation)
    • Supports 8-, 4-, and 1-bit weights and activations
    • Programmable Activation Functions
    • Skip Connections
    • Support for Spatio-Temporal and Temporal Event-Based Neural Network
    Block Diagram -- Neuromorphic Processor IP (Second Generation)
  • Neuromorphic Processor IP
    • Supports 4-, 2-, and 1-bit weights and activations
    • Supports multiple layers simultaneously
    • Convolutional Neural Processor (CNP) and
    • Fully-connected Neural Processor (FNP)
    Block Diagram -- Neuromorphic Processor IP
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