112Gb/s SerDes IP
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112G-ELR PAM4 SerDes PHY - TSMC 5nm
- TSMC 5nm FinFET CMOS Process
- Power-optimized for ELR and LR links
- Integrated BIST capable of producing and checking PRBS
- 56-112Gbps PAM4 or 1-56Gbps NRZ data rates
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MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
- Consumer Application SERDES
- From 1.125Gb/s to 8Gb/s/ 10Gbs
- Technology: 28FDSOI 8ML & 10ML
- Support multi lane configuration
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FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- 1P7M/1P8M/1P9M/1P10M layout structure based on 40nm Logic 1P10M Salicide 1.1V/2.5V process.
- 1.1V/2.5V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
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FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- Layout structure based on 1P6M, 1P7M, or 1P8M 0.13um Logic Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
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Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- 1P6M/1P7M/1P8M layout structure based on 0.13um Logic 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
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Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- 1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process.
- 1.2V/2.5V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
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Dual FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @120Hz) LVDS SerDes 10:70 channel decompression with deskew capability
- 1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process
- 1.2V/2.5V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
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FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- 1P7M/1P8M/1P9M/1P10M layout structure based on 65nm Logic 1P10M Salicide 1.2V/2.5V process.
- 1.2V/2.5V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
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Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- • Dual independent single link mode (can drive 2 separate displays with different resolution)
- • 1P8M layout structure based on TSMC 40nm Logic (G/LP) 1P10M Salicide 1.1V/2.5V process.
- • 1.1V/2.5V 10% supply voltage, -40/+125C
- • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
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Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- • Dual independent single link mode (can drive 2 separate displays with different resolution)
- • 1P8M layout structure based on SMIC 40nm Logic LL 1P10M Salicide 1.1V/2.5V process.
- • 1.1V/2.5V +/-10% supply voltage, -40/+125C
- • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.