FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability

Overview

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).

Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 5.95Gb/s (744Mbytes per second).

Two (2) instances can provide Full-HD @120hz (3DTV) support.

Key Features

1P7M/1P8M/1P9M/1P10M layout structure based on 40nm Logic 1P10M Salicide 1.1V/2.5V process.
1.1V/2.5V ±10% supply voltage, -40/+125°C
Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
+/-0.3 UI bus de-skew, relaxes timing constraint
Input clock detector (self reset when missing clock)
Spread-spectrum input clock support (can be used in SS systems)
Core cell area : [contact us]
Power consumption [contact us] @150Mhz
Built-in power pads with ESD protection.
Low leakage power-down mode <1uA.

Benefits

support full HDTV @120hz (3DTV)
Lowest bounding pad count
Low cost IP
reliability
highly adjustable
customization for your own design

Deliverables

Design kit includes :

LEF view and abstract gdsII
Verilog HDL behavioral model
Liberty (.lib) timing constraints for typical, worse and best corner case
Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Tapeout kit includes the design kit plus plysical view:

gdsII
LVS netlist and report
DRC/ERC/ESD/ANT report

Technical Specifications

Maturity

please contact us

Availability

please contact us

SMIC

Pre-Silicon: 40nm LL

TSMC

Pre-Silicon: 40nm G , 40nm LP

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