FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability

Overview

This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).

Thanks to its innovative lane to lane de-skew mechanism this macro can operate up to a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gb/s, providing a total maximum bandwidth of 5.95Gb/s (744Mbytes per second)

Two (2) instances provides full HDTV @120hz (3DTV) support.

Key Features

Layout structure based on 1P6M, 1P7M, or 1P8M 0.13um Logic Salicide 1.2V/3.3V process.
1.2V/3.3V ±10% supply voltage, -40/+125°C
Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
+/-0.3 UI bus de-skew, relaxes timing constraint
Input clock detector (self reset when missing clock)
Spread-spectrum input clock support (can be used in SS systems)
Core cell area [contact us]
Power consumption [contact us] @150Mhz
Built-in power pads with ESD protection.
Low leakage power-down mode <1uA.

Benefits

Two (2) instances support full HDTV @120hz (3DTV)
Lowest bounding pad count
Low cost IP
reliability
highly adjustable
customization for your own design

Deliverables

Design kit includes :

LEF view and abstract gdsII
Verilog HDL behavioral model

Liberty (.lib) timing constraints for typical, worse and best corner case

Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Tapeout kit includes the design kit plus plysical view:

gdsII
LVS netlist and report
DRC/ERC/ESD/ANT report

Technical Specifications

Maturity

please contact us

Availability

now

SMIC

Pre-Silicon: 130nm G , 130nm LL

Silterra

Pre-Silicon: 130nm

TSMC

Pre-Silicon: 130nm G , 130nm LP

UMC