112G-ELR PAM4 SerDes PHY - TSMC 5nm

Overview

112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels for HPC SoCs.

The Cadence 112Gbps Multi-Rate Extended Long-Reach (ELR) PHY IP for TSMC 5nm operates at 56-112Gbps using PAM4 modulation or 1-56Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The ELR PHY provides additional performance margin to high-loss and reflective channels by incorporating reflection cancellation and enhanced digital signal processing. The area- and poweroptimized design is ideal for high port-density applications that require ELR performance.

Key Features

TSMC 5nm FinFET CMOS Process
Power-optimized for ELR and LR links
Integrated BIST capable of producing and checking PRBS
56-112Gbps PAM4 or 1-56Gbps NRZ data rates
Compact footprint for high-density designs
Fully autonomous startup and adaptation without requiring ASIC intervention
Best-in-class DSP supports ELR lossy and reflective channels
Small area and low power is ideal for high port-density applications
Beach-front optimized floorplan allows north-south and east-west SoC edge placement
Comprehensive on-chip diagnostic features make system testing/debugging quick and easy

Applications

Communications
Data Processing

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist and Verilog models of I/O pads, and RTL for all PHY modules
Verilog models of I/O pads, and RTL for all PHY modules
STA scripts for use at chip or standalone PHY levels
Verilog testbench with memory model, configuration files, and sample tests

Technical Specifications

Foundry, Node

TSMC 5nm

Maturity

Silicon proven

TSMC

Silicon Proven: 5nm

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