The interrupt controller monitors interrupts from all other modules within the system and issues interrupt requests to the processor when necessary. The interrupt controller is scalable to support from 1 to 32 interrupt sources. It also provides enable set and enable clear mechanisms to prevent dangerous read-modify-write operations. It provides active high & active low IRQ & FIQ interrupt request outputs.
APB Interrupt Controller
Overview
Key Features
- AMBA® APB Compatible
- Up to 32 independent interrupt sources
- FIQ and IRQ outputs
- Single bit enable and clear control
Block Diagram
Deliverables
- Verilog Source
- Complete Test Environment
- APB Bus Functional Model
Technical Specifications
Maturity
Silicon Proven
Availability
Now
Related IPs
- Interrupt controller with APB interface
- APB General Purpose IO (w/ interrupt)
- APB I2C Master/Slave Controller
- An APB slave peripheral that can be used to control interrupts of devices when that send interrupts to CPU
- Programmable Interrupt Controller
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP