8259A Interrupt Controller

Overview

8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.

Key Features

  • Eight interrupt request input per chip
  • Up to 64 interrupt request inputs per system
  • Edge or level triggered interrupt request inputs
  • Individually maskable interrupt requestsProgrammable interrupt request priority orders
  • Polling operation capability
  • Extended mode with cascade connection of external interrupts
  • Supports Slave mode in extended mode

Benefits

  • Can be used to assign priority levels to interrupt outputs
  • Allows cascading of multiple interrupts

Block Diagram

8259A Interrupt Controller Block Diagram

Applications

  • Core is designed to use with industry standard microprocessors such as 80286, 8086/8088, 8080/85.

Deliverables

  • ..

Technical Specifications

Maturity
Not Applicable
Availability
Available
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Semiconductor IP