Pipeline SDRAM Controller

Key Features

• Designed with synthesizable HDL for ASIC and PLD synthesis.
• Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
• Supports register mode and non-register mode SDRAM DIMM.
• Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
• Pipeline access allows continues data transfer without wasted cycle.
• Supports column-only access on page hit.
• Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
• Programmable word size:16, 32 and 64 bits.
• Supports all burst lengths: 1, 2, 4, 8 and full page.
• Zero wait state burst data transfer.
• Programmable SDRAM access timing parameters.
• Automatic refresh generation with programmable refresh intervals.
• Programmable memory configuration registers.
• Supports external data buffer between user device and SDRAM data bus by pro-viding a transmit/receive signal.

Technical Specifications