IP Catalog > Memory Controller/PHY IP > Other > xSPI Multiple Bus Memory Controller

xSPI Multiple Bus Memory Controller

Overview

The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0  –  OctaBus™  –  Xccela® Bus  –  Octal Bus JEDEC® xSPI (JESD251) Profile 1.0 and Profile 2.0, …

 

SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.

JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.

SLL’s official partners include many of the leading global memory vendors. SLL works closely with our partners to ensure SLL’s memory controllers are physically qualified with their memory device variants, significantly reducing your project’s risks. SLL’s xSPI MBMC is internally verified by SLL with an extensive end-to-end test bench that achieves near 100% code coverage.

SLL’s small xSPI MBMC IP enables you to easily evaluate, select and adopt the benefits of the latest xSPI-style memories in your projects and products.

SLL provides world class pre-sales and post-sales technical support for all the major memory vendors and FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice.

Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.

xSPI MBMC support for FPGA and ASIC targets

This memory controller IP has been ported to, and physically tested on, a broad range of FPGA device variants, including:

  • Most modern Intel FPGA device families, including:
    • Intel MAX 10 – Up to 200 MHz DDR
    • Cyclone IV 
    • Cyclone 10 LP – Up to 200 MHz DDR
    • Cyclone 10 GX – Up to 250 MHz DDR
    • Cyclone V
    • Cyclone V SoC
    • Arria 10 – Up to 250 MHz DDR
    • Arria 10 SoC – Up to 250 MHz DDR
    • Stratix 10 – Up to 250 MHz DDR
  • Most modern Xilinx FPGA device families, including:
    • Artix-7
    • Kintex-7
    • Virtex-7
    • Zynq 7000
    • Kintex Ultrascale+
    • Zynq Ultrascale+
    • Virtex Ultrascale+ (ideal for supporting ASIC design prototyping in FPGA)
  • Microchip (Microsemi)
    • PolarFire FPGA – Up to 250 MHz DDR

This memory controller IP is also currently being ported from FPGA to standard cell ASIC at up to 250 MHz DDR with x4/x8/x16 datapath support.

xSPI MBMC support for memory devices

SLL’s memory controller supports, and is physically qualified with, the broadest range of JEDEC xSPI Profile 1.0 and 2.0 and xSPI-like memory device variants in the market.

  • Supports PSRAM (low power replacement for SDR, LPSDR, DDR and CellularRAM)
  • Supports NOR Flash (for fast random read access and long term data retention)
  • Support for NAND Flash coming soon (for low-cost per bit and largest storage capacities)
  • Supports memory devices with x4, x8 and x16 data paths
  • Supports mixing-and-matching memory types {PSRAM, PSRAM}, {NOR Flash, PSRAM}, {NOR Flash, NOR Flash} with the same data path width on shared pins
  • Supports use of different bus protocols, such as {HyperBus 1.0, OctaBus}, {JEDEC xSPI Profile 1.0, HyperBus 2.0} on shared pins
  • Use of selected x8 non-volatile devices for power on configuration of Intel Cyclone 10 LP in 1S-1S-1s mode, and high speed re-use of that memory device in 8D-8D-8D mode to reduce bill of materials and increase system performance

SLL’s xSPI MBMC supports the broadest range of memory vendors:

  • Ensures both short term and long term availability of memory devices for your project
  • The ability to source memory devices, from all major memory vendors, reduces your supply chain risk

xSPI MBMC currently supports, or will very soon support:

  • AP Memory® Xccela™ PSRAM, OctaRAM™ and QSPI DDR PSRAM
  • Infineon® (Cypress®) HyperFlash™ 1.0
  • Everspin® SPI Industrial STT-MRAM Persistent Memory (EM064LX)
  • Gigadevice® NOR Flash (GD25X, GD25LX)
  • Infineon® HyperRAM™ 2.0 with HyperBus™ Interface and HyperRAM™ 2.0 with Octal Interface
  • Infineon® Semper™ Flash with HyperBus™ Interface and Semper™ Flash with Octal Interface
  • Integrated Silicon Solution Inc.® (ISSI) HyperRAM™ 1.0 (Revision D dies or higher only), HyperRAM 1.0™ with inbuilt ECC  and HyperFlash™ 1.0
  • ISSI® x8 Octal RAM and Octal RAM with inbuilt ECC
  • ISSI® x8 Octal Flash (NOR Flash)
  • ISSI® x8 Octal MCP
  • Jeju Semiconductor Corp® (JSC) OctaRAM™
  • Macronix® OctaBus™ / OctaFlash™ (NOR Flash)
  • Micron® Xccela™ Flash (NOR Flash)
  • Winbond® HyperRAM™ 1.0, 2.0 and 3.0
  • Winbond® OctalNAND for use with Linux (W35N01JW, W35N02JW, W35N04JW)

xSPI MBMC enables easy transition from HyperBus™ 1.0 to HyperBus™ 2.0.
SLL’s HyperBus™ 1.0 customers are already successfully employing 200 MHz HyperBus™ 2.0 devices at up to 200 MHz DDR in FPGA.

Key Features

  • Includes tight integration with all the major FPGA vendor’s graphical system integration tools (Platform Designer, Vivado, …)  
  • Features high quality local interconnect, with support for the following interconnect protocols:
    • ARM AMBA AXI4 protocol
    • ARM AMBA APB3 protocol
    • Intel Avalon-MM protocol
    • other interconnect protocols available on request…
  • Includes internal clock-crossing circuitry between the local bus interconnect and the external memory channel to reduce circuit area and improve the performance of the customer’s design
  • Excellent memory access performance for both latency sensitive and bandwidth intensive applications:
    • The round trip time for read memory transfer requests through the memory controller has been optimized for latency sensitive applications, such as processor cores.
    • The memory controller supports long burst memory transfer requests over the memory channel to sustain high effective memory bandwidth (>90% efficiency of memory channel)
    • Note:  SLL offers a range of cache technologies to significantly increase the performance of  processor cores that do not have internal instruction and/or data caches when accessing external memories.
  • Features low circuit area and low SRAM usages, making SLL’s memory controller viable for use in resource constrained designs. 
  • Includes optional support for automatic configuration of memory devices at power on:
    • FPGA customers typically use the automatic configuration option
    • This dramatically simplifies integration of SLL’s memory controller in customer designs, enabling all firmware to be executed in place from x8 NOR Flash.  
  • Include support for manual configuration of the memory controller and any attached memory devices
    • ASIC customers typically use the manual configuration option
    • ASIC customers can prototype their designs in FPGA with manual configuration option enabled
  • Supports x4, x8 and x16 data path width in a single instantiation of SLL’s memory controller IP
  • Supports 2 or more instantiations of the memory controller IP in one project
    • Preliminary support for splitting AXI4 requests across 2 instances of the memory controller in parallel to double memory bandwidth is now available

Block Diagram

xSPI Multiple Bus Memory Controller Block Diagram

Technical Specifications

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