eMMC Host Controller IP

Overview

The eMMC Host controller IP is a highly integrated host controller IP solution that supports three key memory card I/O technologies:

eMMC 4.51
SD 3.0
SDIO 3.

The eMMC Host controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The eMMC 4.51 Host IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.

Key Features

Compliances

eMMC Spec v4.51
SD Host Controller Spec v3.0* (SDXC)
SDIO Spec v3.0
SD Memory Spec v3.01
eSD Memory Spec v2.1

IP Details

Supports eMMC4.51 Security Protocol Commands
Supports Standard Capacity (SDSC), High Capacity (SDHC) and Extended Capacity (SDXC) cards
Supports all UHS-I Operation Modes (DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50)
Supports UHS50 and UHS104 cards
Supports MMCPlus™ and MMCMobile™ cards
Supports Clock Tuning Mechanism
Host clock rate variable between 0 and 208 MHz for SD and upto 200 MHz for eMMC
Boot capability to boot directly from SD, eMMC cards
Up to 104MBytes/sec read and write rates with 4 parallel SD data lines.
Up to 200MBytes/sec read and write rates with 8 parallel MMC data lines.
Supports HS 200 mode for eMMC 4.51 devices
Supports Test Register to generate events by software
Supports non-DMA, SDMA, ADMA1, and ADMA2 modes
Supports both normal Boot mode and Alternate Boot Operation mode
Supports Hardware Reset Signal.
Supports Wakeup mechanism.
Card detection (insertion / removal) during power down or when clock is turned off
Password protection of cards
Supports 1 and 4-bit SD modes and 1/4/8-bit MMC modes
Supports multi media card interrupt mode
Supports eMMC 4.51 features such as 4KB sector size, Packed commands, RTC, Context ID, Data tag, Sanitize, Discard operations
Optional support for multiple slots
Allows card to interrupt host in 1-bit, and 4-bit SD modes
Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
Error Correction Code (ECC) support for MMC4.x cards
Designed to work with I/O cards, read-only cards and read/write cards.
Supports read wait control, suspend/resume operation
Optional support for SPI mode to handle legacy SD, MMC cards

Benefits

RTL design in Verilog
UHS-I PHY GDSII
Easy-to-use test environment
Synthesis scripts
Technical documentatio

Block Diagram

Deliverables

RTL design in Verilog
UHS-I PHY GDSII
Easy-to-use test environment
Synthesis scripts
Technical documentation

Technical Specifications

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