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DDR2 IP

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Search (12)
Compare 12 DDR2 IP from 7 vendors (1 - 10)
  • DDR SDRAM Controller
    • Supports industry standard Double Data Rate (DDR) SDRAM.
    • Designed for ASIC and FPGA implementations in various system environments.
    • Programmable memory size and data width.
    • Supports industrial standard 64Mbit, 128Mbit and 256Mbit DDR SDRAMs.
    Block Diagram -- DDR SDRAM Controller
  • NAND Flash Controller
    • Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
    • Supports 1, 4 and 8 bit ECC correction per 512byte.
    • Uses Hamming code for SLC and BCH code for multi-bit correction in MLC.
    • Programmable support for large block and small block NAND Flash devices with 512, 2k and 4k byte page sizes.
    Block Diagram -- NAND Flash Controller
  • DDR2 SDRAM Controller
    • Supports industrial standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
    • Page hit detection to support multiple column accesses within the same row.
    • Pipeline access enables continuous data bursting and hidden active commands, even in the case of page misses.
    • Issue precharge, active and read/write commands to multiple banks at the same time.
    Block Diagram -- DDR2 SDRAM Controller
  • QDR2 Synthesizable Transactor
    • Supports 100% of QDR2 protocol standard CY7C1314CV18
    • Supports separate independent read and write data ports with concurrent read and write operation
    • Supports full data coherency, providing most current data
    • Supports synchronous pipeline read with self-timed late write
    Block Diagram -- QDR2 Synthesizable Transactor
  • GDDR2 Synthesizable Transactor
    • Supports 100% of GDDR2 protocol standard
    • Supports all the GDDR2 commands as per the specs
    • Supports all types of timing and protocol violation detection
    • Supports all mode registers programming
    Block Diagram -- GDDR2 Synthesizable Transactor
  • Avalon Mobile DDR Memory Controller
    • 200 MHz Cyclone / Stratix memory performance
    • Supports all standard Mobile DDR SDRAM devices
    • 1 to 16 Avalon® independent local bus port interfaces
    • Avalon Pipelined and Burst transfers
    Block Diagram -- Avalon Mobile DDR Memory Controller
  • Gen 2 DDR multiPHY IP
    • Support for JEDEC standard LPDDR2, LPDDR3, and DDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR3-2133
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell components allows precise control of timing critical delay and skew paths
    Block Diagram -- Gen 2 DDR multiPHY IP
  • DDR3/2 PHY - TSMC 40LP25
    • When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
    • Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
    • Support for DDR3L (1.35V DDR3)
    • Support for DDR2 and DDR3 DIMMs
    Block Diagram -- DDR3/2 PHY - TSMC 40LP25
  • Avalon Multi-port DDR2 Memory Controller
    • 200 / 333 MHz (400/666 Mbps) Cyclone/Stratix DDR2 memory performance
    • DDR2 Memory Devices
    • From 1 to 16 Avalon-MM local bus port interfaces
    • Memory bandwidth utilization in excess of 95%
    Block Diagram -- Avalon Multi-port DDR2 Memory Controller
  • DDR1 DDR2 SDRAM Memory Controller
    • Memory Interface
    • Supported Soc Bus Interconnect
    Block Diagram -- DDR1 DDR2 SDRAM Memory Controller
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