DDR SDRAM Controller

Key Features

• Supports industry standard Double Data Rate (DDR) SDRAM.
• Designed for ASIC and FPGA implementations in various system environments.
• Programmable memory size and data width.
• Supports industrial standard 64Mbit, 128Mbit and 256Mbit DDR SDRAMs.
• Provides user data at twice the data width compared to DDR SDRAM data.
• Supports burst size of 2 to 8 words.
• Supports zero wait state burst data transfer to maximize data bandwidth.
• Programmable SDRAM access timing parameters.
• Automatic refresh generation with programmable refresh intervals.
• Optional Error Correction Code (ECC).
• Multiple external DDR SDRAM partitions.
• Fully synchronized design based on user supplied clock.

Deliverables

• netlist
• routing control file
• verilog/vhdl source code
• test vectors
• test benches
• design templates.

Technical Specifications