Low Latency DRAM Synthesizable Transactor

Overview

Low Latency DRAM Synthesizable Transactor provides a smart way to verify the Low Latency DRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's Low Latency DRAM Synthesizable Transactor is fully compliant with standard Low Latency DRAM Specification and provides the following features.

Key Features

Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specifications
Supports 8 internal banks
Supports all mode registers programming
Supports programmable read latency and row cycle time
Supports address multiplexing
Supports all the Low Latency DRAM commands as per the specs
Supports programmable burst lengths
Supports data mask for write commands
Checks for following:

Check-points include power on, initialization and power off rules
State based rules, active command rules
Read/Write command rules etc
All timing violations

Supports power down features
Supports self refresh features
Supports DLL
Supports ODT (on-die termination)
Supports all types of timing and protocol violation detection
Protocol checker fully compliant with Low Latency DRAM specification
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Benefits

Compatible with testbench writing using SmartDV's VIP
All UVM sequences/testcases written with VIP can be reused
Runs in every major emulators environment
Runs in custom FPGA platforms

Block Diagram

Deliverables

Synthesizable transactors
Complete regression suite containing all the Low Latency DRAM testcases
Examples showing how to connect various components, and usage of Synthesizable Transactor
Detailed documentation of all DPI, class, task and function's used in verification env
Documentation contains User's Guide and Release notes

Technical Specifications

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