IP Catalog > Broadcast IP > Error Correction/Detection IP > Forward Error Correction IP > VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter

Overview

The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.

Solution for GPUs, UHD Set-top Boxes, Desktop and Laptop PCs, USB-C/DisplayPort Accessories

Key Features

  • VESA DisplayPort 1.4 compliant
  • Reed-Solomon RS (254,250) FEC, 10-bit symbols
  • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
  • DisplayPort main 8b/10b encoder included (Tx only)
  • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
  • Single unified APB interface supports 4-lane mode (Rx)
  • Performance monitoring and statistics counters (Rx)

Block Diagram

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter Block Diagram

Applications

  • GPUs
  • Desktops & laptops
  • UHD TVs and set-top boxes
  • USB Type-C & DisplayPort products
  • Tablets & mobiles

Deliverables

  • Verilog RTL
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Technical Specifications

Request Info

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