I²C Master

Overview

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.

The I²C-master core is a modified version of the OpenCores I²C-Master where the WISHBONE interface has been replaced with an AMBA APB interface. The core is compatible with Philips I²C standard and supports 7- and 10-bit addressing. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.

Key Features

  • AMBA APB interface
  • Supports 7- and 10-bit addressing
  • Bus arbitration (multi master operation)
  • Software programmable clock frequency
  • Clock stretching

Block Diagram

I²C Master Block Diagram

Technical Specifications

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Semiconductor IP