The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB. The core is compatible with the Philips I²C standard and supports 7- and 10-bit addressing with an optionally software programmable address. Standard-mode (100 kb/s) and Fast-mode (400 kb/s) operation are supported directly.
I²C Slave
Overview
Key Features
- AMBA APB interface
- Optional programmable I²C address - The initial address is configurable via a VHDL generic. The designer can choose to leave the core's address programmable via an APB mapped register.
- 10-bit address support. If the core is configured without a hard coded address software may also configure the core to use 7-bit addressing.
- Four main modes, core can be configured to force a master into wait mode by lowering the SCL line during reception and/or transmission. See GRIP manual for details.
- Clock stretching
Block Diagram
Technical Specifications
Related IPs
- I2C Master and Slave
- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
- I2C Controller IP – Slave, User Register Interface, No CPU Required
- I2C Controller IP – Master / Slave, Parameterized FIFO, Hs-Mode (3.4 Mbps) AXI/AHB/APB/Avalon Buses