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Interface IP for UMC

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Compare 366 Interface IP for UMC from 23 vendors (1 - 10)
  • 125Mbps to 16Gbps Multi-protocol SerDes PMA
    • Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
    • Extremely low jitter suitable for Enterprise SerDes applications
    Block Diagram -- 125Mbps to 16Gbps Multi-protocol SerDes PMA
  • 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
    • Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
    • Extremely low jitter suitable for Enterprise SerDes applications
    Block Diagram -- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI Specification for D-PHY Version 1.2
    • Supports MIPI Specification for C-PHY Version 1.0
    Block Diagram -- MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
  • PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
  • I2C Master Serial Interface Controller
    • I2C-compatible interface
    • AMBA AXI4-Lite bus
    • Standard and custom data rates
    • Configurable setup/hold times
    Block Diagram -- I2C Master Serial Interface Controller
  • I2C Master Serial Interface Controller
    • I2C-compatible interface
    • AMBA APB3 bus
    • Standard and custom data rates
    • Configurable setup/hold times
    Block Diagram -- I2C Master Serial Interface Controller
  • MIPI D-PHY Universal IP in UMC 40LP
    • Consists of 1 Clock lane and up to 4 Data lanes
    • Supports the MIPI Standard 1.1 for D-PHY
    • Supports both high speed and low-power modes
    Block Diagram -- MIPI D-PHY Universal IP in UMC 40LP
  • DDR4 multiPHY - UMC 28HPC18
    • Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
    • Scalable architecture that supports data rates up to DDR4-2667
    • Support for DIMMs
    • Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
    Block Diagram -- DDR4 multiPHY - UMC 28HPC18
  • LPDDR4 multiPHY V2 - UMC 28HPC+18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - UMC 28HPC+18
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