PowerPC to PCI Bridge

Key Features

Fully supports PCI specification 2.1 and 2.2 protocol.
Designed for ASIC and PLD implementations.
Fully static design with edge triggered flip-flops.
Supports all PowerPC CPU with 603 bus interface and MPC860 interface.
Host bridge design includes bus master, bus target and central system functions.
Generates standard PCI type 0 and type 1 configuration accesses.
Combined bus master and target functions.
Master function
- Initiate PCI memory and IO read/write
- Automatic transfer restart on target retry and disconnect
- Target function
  - Memory or IO read/write
  - Configuration read/write
  - Support for back-end initiated target retry, disconnect and abort
Supports Zero wait state and user inserted wait state burst data transfer.
Dual write buffer supports write data posting.
User controlled burst and non-burst data transfer.
Automatic handling of configuration register read/write access.
Supports user initiated target retry, disconnect, abort and delayed transaction.
Parity generation and parity error detection.
Includes all PCI specific configuration registers.
Supports high speed bus request and bus parking.
Differentiating Features
- CPU type and CPU bus interface selection.
- Bus arbiter.
- Multiple base address registers.
- Asynchronous clock domain.
- Unidirectional host bridge.

Short description

Vendor

Vendor Name

Foundry, Node

ASIC and FPGA

Availability

Now

UMC

Pre-Silicon: 500nm