PowerPC Bus Arbiter

Key Features

• Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
• Designed for ASIC or PLD implementations in various system environments.
• Fully static design with edge triggered flip-flops.
• Supports up to eight PowerPC bus masters with unlimited slave device support.
• Supports two outstanding bus accesses.
• Supports address only transfer and address bus retry.
• Independent address bus and data bus tenure with separate bus grant and data bus grant.
• Option for fixed priority assignment or rotating priority scheme

Block Diagram

Technical Specifications