Free-running on-chip oscillator

Overview

Low power relaxation oscillator is a programmable free-running clock generator for coarse clock generation. The design uses a relaxation oscillator with fully integrated elements so no external components are required. The oscillator is designed to have excellent supply noise rejection so it is ideal for use in noisy SoC environments.

Key Features

Glitch-free frequency programmability to calibrate out process variations Frequency accuracy as good as 1.5% over voltage, temperature, and process aging after initial calibration
Low sensitivity to supply voltage and temperature changes
Fast initial settling time
Low power operation -- below 100uW and as low as 20uW in some processes
Low period jitter
Low area

Benefits

Compact and low power
No external components
Baseline CMOS logic process masks only
Excellent frequency precision over PVT after trimming

Block Diagram

Deliverables

GDSII
CDL Netlist (MG Calibre Compatible)
Functional Verilog Model
Liberty timing models (.lib)
LEF
Application Note

Technical Specifications

Foundry, Node

TSMC, GF, SMIC, UMC, ... 7nm, 10nm, 16nm, 28nm, 40nm

Maturity

Silicon Proven, Production

Availability

Available Now

GLOBALFOUNDRIES

In Production: 28nm SLP

SMIC

Silicon Proven: 40nm LL

TSMC

In Production: 5nm , 7nm , 10nm , 12nm , 16nm , 28nm HPC , 28nm HPCP , 40nm LP
Pre-Silicon: 28nm HPM , 40nm LP
Silicon Proven: 3nm , 6nm

UMC

In Production: 40nm LP

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