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AES IP for TSMC

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Compare 12 AES IP for TSMC from 3 vendors (1 - 10)
  • Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
    • Encrypts using the AES Rijndael Block Cipher Algorithm.
    • Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST). FIPS-197 validated (AESAVS).
    • Processes 128-bit data blocks with 8, 16 or 32-bit data interface
    • Employs key sizes of 128 bits (AES128), 192, or 256 bits (AES256)
    Block Diagram -- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
  • 802.15.3 CCM AES Core
    • Small size: From 9,500 ASIC gates at 802.15.3 data Speeds.
    • High data rate: up to 8 Gbps for IEEE 802.15.3c / ECMA-387 (TC 48) / IEEE 802.11ad 60 GHz PHY
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    Block Diagram -- 802.15.3 CCM AES Core
  • 802.11i CCMP/TKIP IP Core
    • Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication with the CCMP protocol and RC4/”Michael” cipher for the TKIP.
    • The WPA3 core is tuned for high data rate 802.11i applications (up to 2 Gbps for the CCMP protocol for 802.11n/802.11ac).
    Block Diagram -- 802.11i CCMP/TKIP IP Core
  • High speed low latency AES-GCM pipeline, 100Gbps
    • The AES-IP-61 (EIP-61) is IP for accelerating AES-GCM based cryptographic solutions.
    • Designed for easy integration and very high performance the AES-IP-61 crypto accelerator provide a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed processing pipelines.
    Block Diagram -- High speed low latency AES-GCM pipeline, 100Gbps
  • AES “All Modes” Accelerators
    • The AES-IP-39 (EIP-39) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting all NIST modes including ECB, CBC, CTR, CFB, OFB, CCM, GCM, CBC-MAC, CMAC, XTS, F8, F9 modes of operation up to 6.4 Gbps @ 1GHz.
    • Designed for fast integration, low gate count and full transforms, the AES-IP-39 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into security modules needing versatile crypto.
    Block Diagram -- AES “All Modes” Accelerators
  • AES XTS/GCM Accelerators
    • Wide bus interface
    • Basic AES encrypt and decrypt operations
    • Key sizes: 128, 192 and 256 bits
    • Key scheduling in hardware, allowing key, key size and 
direction changes every 13/15/17 clocks with zero impact 
on throughput
    • Hardware reverse (decrypt) key generation
    Block Diagram -- AES XTS/GCM Accelerators
  • AES Key Wrap Accelerators
    • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
    • Key/KEK sizes: 128, 192 and 256 bits
    • Includes key scheduling hardware
    • Supported modes: NIST AES Key Wrap
    • Memory interface for key, intermediate and result data storage up to 4096 bits 
(Maximum supported input data block size is 512 bytes) 

    Block Diagram -- AES Key Wrap Accelerators
  • AES ECB/CBC/CTR Accelerators
    • The AES-IP-36 (EIP-36) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting ECB, CBC and CTR modes up to 12.8 Gbps @ 1GHz.
    • Designed for fast integration, low gate count and full transforms, the AES-IP-36 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high speed crypto pipelines.
    Block Diagram -- AES ECB/CBC/CTR Accelerators
  • NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
    • Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197).
    • Supports both encryption and decryption functions.
    • Supports 128/192/256-bit Cipher keys.
    • Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively.
    Block Diagram -- NIST FIPS-197 Compliant Ultra-Low Power AES IP Core
  • 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
    • 8,900 ASIC gates at 802.11a/g OFDM data speeds
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    • Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC, AES0CTR per NIST SP800-38C)
    Block Diagram -- 802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
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