Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core

Overview

The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data blocks with 128-bit key (a 256-bit key version is available).

Basic core is designed only for encryption and is the smallest available on the market (less than 3,000 gates). Enhanced versions are available that support encryption and decryption for various NIST cipher modes (ECB,CBC, OFB, CFB, CTR), as well as different datapath widths for size/performance tradeoff. The core includes the key expansion logic.

The design is fully synchronous and available in both source and netlist form.

Optional data integrity and differential power attack resistance features.

Key Features

Encrypts using the AES Rijndael Block Cipher Algorithm.
Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST). FIPS-197 validated (AESAVS).
Processes 128-bit data blocks with 8, 16 or 32-bit data interface
Employs key sizes of 128 bits (AES128), 192, or 256 bits (AES256)
Includes the key expansion function
Optional parity check feature for data integrity
Optional additive data masking throughout the core (including the Sbox additive masking) for strong differential power attack (DPA) resistance
Optional cycle hiding for DPA resistance
Simple, fully synchronous, reusable design
Completely self-contained: does not require external memory
Available as fully functional and synthesizable Verilog or VHDL, or as a netlist for popular programmable devices and ASIC libraries
Deliverables include self-checking test benches

Benefits

Extremely compact design (less than 3K gates for TSMC 0.18 process)

Block Diagram

Applications

Cipher for wireless communications, including IEEE 802.11i (Wi-Fi), IEEE 802.15.3, IEEE 802.15.4 (Zigbee), MBOA (WiMedia), 802.16e, Wibree, sensor networks ("smart dust"), motes
Electronic financial transactions
Power line networks
Digital Rights Management (DRM) including Digital Cinema System Specification (DCSS) and High-bandwidth Digital Content Protection (HDCP 2.0)
Secure video surveillance systems
Encrypted data storage
Secure RFID, immobilizers
Secure Smart Cards
ITU H.235
Secure RTP (SRTP, RFC 3711)

Deliverables

HDL Source Licenses

Synthesizable Verilog RTL source code
Testbench (self-checking)
Test vectors
Expected results
Simulation script
Synthesis script
User Documentation

Technical Specifications

Foundry, Node

TSMC

Maturity

Released

Availability

Now