AES “All Modes” Accelerators

Overview

The AES-IP-39 (EIP-39) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting all NIST modes including ECB, CBC, CTR, CFB, OFB, CCM, GCM, CBC-MAC, CMAC, XTS, F8, F9 modes of operation up to 6.4 Gbps @ 1GHz. Designed for fast integration, low gate count and full transforms, the AES-IP-39 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into security modules needing versatile crypto.

The AES-IP-39 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the lightweight configuration of the AES-IP-39 is the cipher core embedded in all Vault-IP platform security engines as well as the Crypto-IP-120 DMA crypto core. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 1 to 6.4 Gbps depending on the configuration and area. Gate count is between 27K and 45K gates depending on the configuration.

The AES-IP-39 can be provided with counter measures including ones against side-channel attacks and fault injection attacks.

Key Features

32-bit register interface
Key sizes: 128, 192 and 256 bits
Includes key scheduling hardware
Feedback modes: ECB, CBC, CTR, OFB-128,  CFB-128
Protocol modes: CCM, GCM, CMAC and XCBC-MAC
Optional modes: AES-XTS, OFB, f8 and f9
Fully synchronous design
Low Speed, Medium Speed, High Speed versions
Optional counter measures against side channel attacks and fault injection attacks
Standard Compliance: FIPS-197, NIST-SP800-38A/B/C/D/E

Benefits

High-speed AES-CCM solution
Silicon-proven AES implementation
Fast and easy to integrate into SoCs
Flexible layered design
Complete range of configurations
World-class technical support

Block Diagram

Applications

IoT security

Deliverables

Documentation

Hardware Reference and Programmer Manual
Integration Manual
Verification Specification

Synthesizable Verilog RTL source code
Self-checking RTL test bench, including test vectors and expected result vectors
Simulation scripts
Configurations:

EIP-39b

High-speed CCM
35k gates
5.81 bits/clk (CCM), 12.8 bits/clk (Other)
up to 550 MHz

EIP-39d

Medium-speed CCM
29k gates
1.93 bits/clk (CCM), 4.00 bits/clk (Other)
up to 700 MHz

EIP-39f

Low-speed CCM
27k gates
1.20 bits/clk (CCM), 2.46 bits/clk (Other)
up to 700 MHz

EIP-39b-g-(-buf or -nobuf)

High-speed CCM+GCM
-buf: 46k gates, -nobuf: 45k gates
11.63 bits/clk (CCM), 5.81 bits/clk (GCM), 12.8 bits/clk (Other)
up to 550 MHz

EIP-39d-g-(-buf or -nobuf)

Medium-speed CCM+GCM
-buf: 36k gates, -nobuf: 34k gates
3.87 bits/clk (CCM), 1.93 bits/clk (GCM), 4.00 bits/clk (Other)
up to 700 MHz

EIP-39g

Low-speed CCM+GCM
33k gates
2.41 bits/clk (CCM), 1.20 bits/clk (GCM), 2.46 bits/clk (Other)
up to 700 MHz

EIP-39f-f8-x

Low-speed CCM+XTS+f8
28k gates
1.20 bits/clk (CCM), 2.46 bits/clk (Other)
up to 700 MHz

Technical Specifications

Foundry, Node

Any

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 7nm , 16nm , 28nm , 40nm G

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