AES Key Wrap Accelerators

Overview

The AES-IP-37 (EIP-37) is IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394) up to 6 Gbps. Designed for fast integration, low gate count and full transforms, the AES-IP-37 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoCs that need high speed key wrap and (key) storage or key import and export systems.

The AES-IP-37 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance ranges from 1 to 6 Gbps depending on the configuration and area. Gate count is between 33K and 62K gates (excluding memory) depending on the configuration. Multiple AES-IP-37 cores can be cascaded.

Key wrap performance of the low gate count version is around 100K key wraps of unwraps (for 80-Byte key data), for the high end it is around 500K to 700K depending on frequency.

Key Features

  • Wide bus interface (128-bit data, 256-bit keys) or 32-bit register interface
  • Key/KEK sizes: 128, 192 and 256 bits
  • Includes key scheduling hardware
  • Supported modes: NIST AES Key Wrap
  • Memory interface for key, intermediate and result data storage up to 4096 bits 
(Maximum supported input data block size is 512 bytes) 

  • Fully synchronous design
  • Low Speed, Medium Speed, High Speed versions
  • Support for two ECC (Error Correcting Code) bits from the external memory
  • Multiple IV loading options 

  • Unwrap result verification



Benefits

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Block Diagram

AES Key Wrap Accelerators Block Diagram

Applications

  • Key encryption
  • Key protection

Deliverables

  • Documentation
    • Hardware Reference and Programmer Manual
    • Integration Manual
    • Verification Specification
  • Synthesizable Verilog RTL source code
  • Self-checking RTL test bench, including test vectors and expected result vectors
  • Simulation scripts
  • Configurations:
    • EIP-36b
      • High-speed Encrypt/Decrypt
      • 62k gates (excluding external memory)
      • 11.6 bits/clk
      • up to 400 MHz
    • EIP-36d
      • Medium-speed Encrypt/Decrypt
      • 39k gates (excluding external memory)
      • 3.88 bits/clk
      • up to 450 MHz
    • EIP-36f
      • Low-speed Encrypt/Decrypt
      • 33k gates (excluding external memory)
      • 2.42 bits/clk
      • up to 450 MHz

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven: 7nm , 16nm , 28nm , 40nm G
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Semiconductor IP