IP Catalog > Foundries > TSMC > Peripheral IP

Peripheral IP for TSMC

Welcome to the ultimate Peripheral IP for TSMC hub! Explore our vast directory of Peripheral IP for TSMC
All offers in Peripheral IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (34)
Compare 34 Peripheral IP for TSMC from 15 vendors (1 - 10)
  • Display Controller - LCD / OLED Panels (AXI4 Bus)
    • Advanced display processing, such as Multi-layer Overlay Windows with composition features such as Alpha Blending, Color Space Conversion, 4:2:0 and 4:2:2 YCrCb color with Re sampling & conversion to RGB, Frame Buffer Compression and Hardware Cursor
    Block Diagram -- Display Controller - LCD / OLED Panels (AXI4 Bus)
  • Display Controller - LCD / OLED Panels (AHB Bus)
    • The DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel.
    • In an FPGA, ASIC, or ASSP device, the microprocessor is an ARM processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
    Block Diagram -- Display Controller - LCD / OLED Panels (AHB Bus)
  • Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
    • The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and 2K Digital Cinema Initiative (DCI) High Definition TFT LCD panel
    • The video image in frame buffer memory can be 8/10/12-bit YCrCb or RGB, with a Color Space Convert to match the source video to the TFT LCD panel requirements

     

    Block Diagram -- Display Controller – 4K Digital Cinema LCD Panels (AXI4/AXI Bus)
  • 0.035... 100 MHz intermediate-frequency amplifier
    • TSMC 65 nm CRN65LP technology
    • Differential inputs, outputs
    • High frequency 0.035 – 100 MHz
    • High linearity
    Block Diagram -- 0.035... 100 MHz intermediate-frequency amplifier
  • Minimum-area low-power clocking PLL (1st gen)
    • - Super small: 80 x 80 microns!
    • - Very low power: 12-mW
    • - Broad frequency range: 2-GHz
    • - Fast lock
    Block Diagram -- Minimum-area low-power clocking PLL (1st gen)
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
    • 25-180 MHz clock support
    • Up to 1.25 Gbps bandwidth
    • Up to 5.0 Gbps data throughput
    • Full Low power CMOS design
    Block Diagram -- 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
  • 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
    • 25-180 MHz clock support
    • Up to 1.25 Gbps bandwidth
    • Up to 5.0 Gbps data throughput
    • Low power CMOS design
    Block Diagram -- 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
  • 2.5 Gbps Transceiver core
    • 1.6 to 2.5 Gbps operation
    • 1.8V power supply, CMOS design
    • Low power dissipation
    • Minimal external components
    Block Diagram -- 2.5 Gbps Transceiver core
  • SD 4.1 UHS-II PHY for TSMC 12nm FF
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”
×
Semiconductor IP