Register File IP for TSMC

Compare 16 Register File IP for TSMC from 6 vendors (1 - 10)

Memory Compilers
- Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.
Tuneable multi-port register file architecture - TSMC 16FFC
Tuneable multi-port register file architecture - TSMC 22ULL
- Custom Register File Architecture
- Power savings >50%
- Wide operating voltage range
- Tuneable performance: Ultra Low Voltage, High speed operation
- Single rail – interfaces directly to logic
- Supports multiple read/write ports
TSMC CLN16FFC Ultra High Density One Port Register File
- The Ultra High Density One Port Register File operates within voltage range from 0.72 V to 0.88 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 128 bits to 72K bits. The Compiler is divided into 3 groups according to their column selection numbers (Mux=1, 2 or 4).
- Pins and metal layers
- 1P4M (2Xa1Xd_h): 4 metal layers used and top metal is MXd.
- Power mesh supported with M4 pins
Tuneable multi-port register file architecture - TSMC 28HPC+
- Custom Register File Architecture
- Power savings >50%
- Wide operating voltage range
- Tuneable performance
- Single rail – interfaces directly to logic
- Supports multiple read/write ports
GCRAM, the highest-density on-chip embedded memory in standard CMOS
- High-density bitcell offering up-to 2X area reduction over high-density 6T SRAM.
- Full logic compatibility with standard CMOS, no additional process steps or cost.
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler up to 64 k
- Foundry sponsored memory generator
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1. Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2. Extend the battery life
- Leakage reduction thanks to careful design structures,optional retention mode and choice of SVT/HVT periphery
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Ultra high speed
- Up to 580 MHz in worst case for 512x32 cut
- Power reduction features
- Data retention mode at 1.2 V to divide leakage by a factor of 2.5 compared to simple stand by mode
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Ultra high speed
- Up to 580 MHz in worst case for 512x32 cut
- Power reduction features
- Data retention mode at 1.2 V to divide leakage by a factor of 2.5 compared to simple stand by mode

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