Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
Overview
Single Port Register File compiler - TSMC 65 nm LP - Memory optimized for high density and high speed - compiler range up to 40 k
Key Features
- Ultra high speed
- Up to 580 MHz in worst case for 512x32 cut
- Power reduction features
- Data retention mode at 1.2 V to divide leakage by a factor of 2.5 compared to simple stand by mode
- Data retention mode at 0.77 V to divide leakage by a factor of 7 compared to simple stand by mode
- Flexible power routing: connection to the power grid or from the periphery of the instance
- Optional Byte write (MUX 2 and 4) and bit-wise write capability (MUX 8)
- Smart periphery design to reach the highest density
- Up to 50% gain in density versus alternative memory depending on instance configuration
- Designed with the uHD HVt Pushed rule bit cell from foundry
- Easy integration
- MUX options
- Data range flexibility allows easy addition of bits for redundancy or ECC purposes
- Address range flexibility allows easy addition of single rows for redundancy purposes
- The Dolphin quality
- Complete mismatch validation of the memory architecture taking into account local and global dispersion
- Optional BIST for industrial fabrication test of instances
Technical Specifications
Maturity
Pre-silicon
TSMC
Pre-Silicon:
65nm
LP
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