USB IP for TSMC

Compare 4 USB IP for TSMC from 2 vendors (1 - 4)

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USB 2.0 femtoPHY -TSMC N6 18 x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB2.0 Dual-Role PHY, TSMC N7, N/S orientation, type-C (ASIL-B)
- Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
- Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
- Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
USB2.0 Dual-Role PHY, TSMC N6, N/S orientation, type-C (ASIL-B)
- Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
- Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
- Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors