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USB IP for TSMC

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Compare 9 USB IP for TSMC from 3 vendors (1 - 9)
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  • 16nm
  • USB 2.0 PHY
    • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
    • Complies with the UTMI v1.05 specification
    • Multiple reference clock supported from 9.6MHz up to 52MHz
    • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
    • Battery Charging Specification v1.2
    Block Diagram -- USB 2.0 PHY
  • USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 2
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 2
  • USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - TSMC 16FF+LL18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FF+LL18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - TSMC 16FF+GL18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FF+GL18 x1, OTG, North/South (vertical) poly orientation
  • USB2.0 Dual-Role PHY, TSMC 16FFC, N/S orientation, type-C (ASIL-B)
    • Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
    • Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
    • Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
    Block Diagram -- USB2.0 Dual-Role PHY, TSMC 16FFC, N/S orientation, type-C (ASIL-B)
  • USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
    • Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
    • Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
    • Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
    • Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator or external clock source
  • USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
    • Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
    • Low power: as low as 50mW (during high-speed packet transmission)
    • Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
    • Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
  • USB 2.0 femtoPHY in TSMC (16nm, N7) for Automotive
    • Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
    • Low power: as low as 50mW (during high-speed packet transmission)
    • Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
    • Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
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