USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
Overview
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumption. M31 utilizes a whole new design architecture to implement the USB 2.0 IP without sacrificing the performance associated with USB 2.0. The USB 2.0 IP is not only suitable for USB peripherals, but also an optimized solution for SOCs that desire multiple USB ports.
Key Features
- Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
- Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
- Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
- Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator or external clock source
- Integrated PLL to provide a variety of stand-alone clock outputs for USB related applications
Technical Specifications
Foundry, Node
6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm
SMIC
Silicon Proven:
14nm
,
28nm
HKC+
,
40nm
LL
,
55nm
LL
Samsung
Silicon Proven:
65nm
LP
TSMC
Pre-Silicon:
7nm
Silicon Proven: 7nm , 12nm , 16nm , 22nm , 28nm HPCP , 40nm LP , 55nm LP , 55nm ULP , 55nm ULPEF , 65nm GP , 90nm G , 110nm G
Silicon Proven: 7nm , 12nm , 16nm , 22nm , 28nm HPCP , 40nm LP , 55nm LP , 55nm ULP , 55nm ULPEF , 65nm GP , 90nm G , 110nm G
UMC
Silicon Proven:
28nm
HPC
Related IPs
- NVM OTP in TSMC (180nm, 152nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm, 28nm, 22nm, 16nm, 12nm, N7, N6, N5, N4P)
- NVM OTP in GF (180nm, 130nm, 65nm, 55nm, 40nm, 28nm, 22nm, 12nm)
- PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
- USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
- NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
- USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)