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USB IP for TSMC

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Compare 14 USB IP for TSMC from 2 vendors (1 - 10)
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  • 6nm
  • USB4 PHY - TSMC N6 1.8V, North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    Block Diagram -- USB4 PHY - TSMC N6 1.8V, North/South Poly Orientation
  • USB 2.0 femtoPHY -TSMC N6 18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY -TSMC N6 18 x1, OTG, North/South (vertical) poly orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC 6FF x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC 6FF x1 OTG, North/South Poly Orientation
  • USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
    • Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
    • Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
  • USB2.0 Dual-Role PHY, TSMC N7, N/S orientation, type-C (ASIL-B)
    • Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
    • Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
    • Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
    Block Diagram -- USB2.0 Dual-Role PHY, TSMC N7, N/S orientation, type-C (ASIL-B)
  • USB2.0 Dual-Role PHY, TSMC N6, N/S orientation, type-C (ASIL-B)
    • Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
    • Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
    • Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
    Block Diagram -- USB2.0 Dual-Role PHY, TSMC N6, N/S orientation, type-C (ASIL-B)
  • USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
    • Compliant to USB4 Gen3(20G) / Gen2(10G)
    • Support USB4 Gen3 PIPE SerDes (128b/132b) coding
    • Support USB4 Gen2 PIPE SerDes (64b/66b) coding
    • Support PIPE USB3.2 Gen2 (128b/132b) coding
    Block Diagram -- USB4 Gen3 x2-lane PHY, TSMC N6, 1.8V or 1.2V, N/S orientation, type-C
  • USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C
    • Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
    • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
    • Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
    • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
    Block Diagram -- USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C
  • USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
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