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USB IP for TSMC

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Compare 21 USB IP for TSMC from 4 vendors (1 - 10)
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  • 16nm
  • USB 2.0 PHY
    • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
    • Complies with the UTMI v1.05 specification
    • Multiple reference clock supported from 9.6MHz up to 52MHz
    • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
    • Battery Charging Specification v1.2
    Block Diagram -- USB 2.0 PHY
  • USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 2
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 2
  • USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FFC18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - TSMC 16FF+LL18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FF+LL18 x1, OTG, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - TSMC 16FF+GL18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - TSMC 16FF+GL18 x1, OTG, North/South (vertical) poly orientation
  • USB-C 3.1/DP TX PHY for TSMC 16FFC, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC 16FFC, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 16FFC, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 16FFC, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC 16FFC x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC 16FFC x1 OTG, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC 16FF+LL x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC 16FF+LL x1 OTG, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC 16FF+GL x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC 16FF+GL x1 OTG, North/South Poly Orientation
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