Peripheral IP for SMIC

Compare 14 Peripheral IP for SMIC from 7 vendors (1 - 10)

Minimum-area low-power clocking PLL (1st gen)
- - Super small: 80 x 80 microns!
- - Very low power: 12-mW
- - Broad frequency range: 2-GHz
- - Fast lock
LVDS TX+ (Transmitter) in UMC 40LP
- Compatible with TIA/EIA-644 LVDS Standard
- 49 Mbps - 770 Mbps bandwidth/channel
- Up to 3.08 Gbps data throughput
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Full Low power CMOS design
1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 25-180 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5.0 Gbps data throughput
- Low power CMOS design
2.5 Gbps Transceiver core
- 1.6 to 2.5 Gbps operation
- 1.8V power supply, CMOS design
- Low power dissipation
- Minimal external components
eMMC/SDIO/SD
- Compliant with eMMC5.1 specifications, up to 200MHz
- Support HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
- Support Enhanced Strobe in HS400
- Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps
- MIPI DPHY v1-1/MIPI CSI/TIA/EIA-644 LVDS/SLVS-400 compliant
M31 ESD I/O in TSMC 12nm, 16nm, 22nm, 28nm. 40nm, 55nm,90nm,180nm
- High Density Library
- Customized layout and function
- Flexible cell combination
- High ESD robustness analog cells
Dual FPD-link, 30-Bits Color LVDS Receiver, 170Mhz (SVGA/FHD@120Hz) LVDS de-serializer 10:70 channel decompression with automatic de-skew
- Layout structure based on 0.13um Logic 1P6M, 1P7M, or 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3- 1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)