Dual RSDS Transmitter, 30-bit color, 80-400Mb/s (SVGA/Full HDTV@120Hz)

Overview

This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control source (TCON) and Column Drivers of a Flat Panel Display.

The transmitter converts up to 30-bit DDR CMOS data (single pixel 24-bit, single pixel 30-bit, dual pixel 24-bit, dual pixel 30-bit color) into 30 RSDS, (Reduced Swing Differential Signaling) data streams.

At a maximum dual pixel rate of 200Mhz, RSDS data line speed is 400Mbps, providing a total throughput of 12Gbps (1.5GygaBytes per second).

All the data input/output are independent from each other and can be assigned following any partitioning to support all LCD and Plasma display panel system architectures. (RGB, front/back, even/odd, mixed RGB etc…)

Each pixel channel has 3 identical clock outputs. Strength of the RSDS I/Os can be adjusted from 2mA nominal to 4mA in order to support both 100 and 50 termination. Tree extra clock output are also provided.

For convenient routing when TCON is mounted on top or bottom of a display panel, a selectable output data mapping is usually available. LSB or MSB of both channels can be forced to High-Z in order to support 24-bit data color.

This IP can interface with both 1.2V or 3.3V core logic, giving more flexibility for the design.

Key Features

• 40 to 200 Mhz Pixel rate per channel ( 80 to 400 Mb/s SDR input, 80 to 400 Mb/s DDR output)
• 30 DATA + 9 RSDS CLK channels
• Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
• 1P6M layout structure based on 0.13um 1P6M generic logic process.
• 3.3V/1.2V 10% supply voltage, -40/+125C
• Dual pixel architecture up to 12Gbps bandwidth
• Low EMI
• 30 and 24 Bits color & reverse output mapping support
• Self Power-On-Reset feature
• Precise RSDS clock skew adjustment using DLL
• Phase-shifted clock output to core to support additional CD control signals
• Accurate output current digital control
• Built-in power pads with ESD protection
• Low leakage power-down mode <10uA.
• Low power consumption, [contact us] mA nominal
• Very compact cell area : [contact us]

Benefits

Low cost IP
reliability
highly adjustable
customization for your own design
support full HDTV @ 120Hz (3DTV)

Deliverables

Design kit includes :

LEF view and abstract gdsII
Verilog HDL behavioral model
Liberty (.lib) timing constraints for typical, worse and best corner case
Full Datasheet /Application Note with integration guidelines document
Silicon characterization report when available

Technical Specifications

SMIC

Pre-Silicon: 130nm G , 130nm LL

TSMC

Pre-Silicon: 130nm G , 130nm LP

Tower

Pre-Silicon: 130nm

UMC