Memory & Libraries IP for SMIC

Compare 521 Memory & Libraries IP for SMIC from 20 vendors (1 - 10)

LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
LVDS Serializer IP
- The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
- The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
LVDS Transceiver
- Meets or exceeds the TIA/EIA-644 LVDS standard.
- Driver, Receiver, Bias, and Power cells included.
- Greater than 400Mbs data rate.
- 1.8V core voltage, 5V IO voltage.
- Receive fault detection.
- 0.3ns differential pulse skew.
1Kbyte EEPROM with configuration 64p8w16bit
- SMIC EEPROM CMOS 0.18 um
- High density of memory cells
- Writing and erasing data by one high-voltage pulse
- Programming and erase time – 2 ms (determined by specification of the EEPROM SMIC cell)
1024-bit EEPROM IP with configuration 32p2w16bit
- SMIC EEPROM CMOS 0.18 um
- 1024-bite of available memory 16(bit per word) x 2(words per page) x 32(pages) bit
- High density of memory cells
1Kbyte Embedded EEPROM with configuration 64p8w16bit
- SMIC EEPROM CMOS 0.18 um
- 1Kbyte of available memory 16(bit per word) x 8(words per page) x 64(pages) bit
512-bit EEPROM with configuration 16p1w32bit
- SMIC EEPROM CMOS 0.18 um
- High density of memory cells
- Writing and erasing data by one high-voltage pulse
1Kbyte EEPROM (NTLab)
- SMIC EEPROM CMOS 0.18 um
- 1Kbyte of available memory 16(bit per word) x 8(words per page) x 64(pages) bit
LVDS interfaces
- Wide operating range
- High data rates
- Very flexible programmability
- Excellent signal integrity
- TIA/EIA644A LVDS and sub-LVDS compatibility
- Receiver also compatible with LVPECL
512-bit EEPROM (NTLab)
- SMIC EEPROM CMOS 0.18 um
- High density of memory cells
- Writing and erasing data by one high-voltage pulse
- Programming and erase time – 2 ms