IP Catalog > DSP & Math IP > Modulation/Demodulation IP > Other

Other

All offers in Other
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (26)
Compare 26 Other from 15 vendors (1 - 10)
  • APB Pulse Width Modulator
    • The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
    • The frequency of the output waveform is either PCLK/256 or PCLK/4096, depending on whether a 4-bit prescaler is enabled.
    Block Diagram -- APB Pulse Width Modulator
  • Pulse Width Modulator
    • The PWM IP core implements a compact and highly flexible Pulse Width Modulator. The core generates a repeated pattern of pulse trains of run-time configurable period and duty cycle.
    • Those pulse trains can be used in a wide variety of applications including but not limited to motor control and LED dimming. They can also be filtered with a lowpass filter to implement Digital to Analog Converters (DAC).
    Block Diagram -- Pulse Width Modulator
  • DVB-S2X Modulator
    • Compliant with DVB-S2 and DVB-S2X
    • Supports ACM, CCM, and VCM modes
    • Support for short and normal frames (16,200 bits and 64,800 bits)
    • Support for QPSK to 256-APSK
    • Support for very low SNR modes (VLSNR) optional
    Block Diagram -- DVB-S2X Modulator
  • ITU G.704 E1 Framer/Deframer
    • E1 framer/deframer compliant to G.704, G.706, G.732 and O.163 ITU recommendations.
    • Supports CAS and CCS signalling standards.
    • Supports CRC4 based framing standards.
    • User configurable receive and transmit control.
    Block Diagram -- ITU G.704 E1 Framer/Deframer
  • Block Diagram -- ITU G.704 T1 Framer/Deframer
  • Programmable OFDM Channel Estimator
    • Fully configurable, high throughput
    • Programmable pilot patterns
    Block Diagram -- Programmable OFDM Channel Estimator
  • OFDM synchronization unit
    • Programmable cyclic prefix, sub-channelization index.
    • Based on a proprietary modification of Schmidl-Cox synchronization algorithm.
    Block Diagram -- OFDM synchronization unit
  • DVB-S2X NarrowBand Demodulator IP
    • This is single demodulator subsystem compliant DVB-S/S2/S2X satellite standards.
    • It is meant to be integrated in the L2A/L2B SOCs. The single demodulator subsystem is made of several blocks.
    • 1 narrow-band demodulator DVB-S / DVBS2 / DVB-S2X up to 65 Msymb/s.
    • 1 DVB-S FEC (Viterbi, Reed-Solomon, Super FEC)
    Block Diagram -- DVB-S2X NarrowBand Demodulator IP
  • Manchester Encoder / Decoder
    • Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
    • Supplied as human readable VHDL (or Verilog) source code
    Block Diagram -- Manchester Encoder / Decoder
  • DVB-S2X WideBand Demodulator IP
    • Two high-symbol-rate (HSR) demodulators: Maximum baud rate 500 Msymbol/s, Up to two slices each,DVB-S2/S2X and Annex M compliant
    • Up to 8 multi-standard demodulators: S/S2/S2X/DTV
    • Integrated full-band tuners and ADCs
    • High-speed digital multiplexer to connect any tuner to any demodulator
    Block Diagram -- DVB-S2X WideBand Demodulator IP
×
Semiconductor IP