The CMS0009 DVB-T/DVB-H Modulator provides all the necessary processing steps to modulate a single (or pair of hierarchical) transport stream(s) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857 or AD9957. Optionally the output can be selected as an IF to supply a single DAC.
The design has been optimised to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx
A description of the processing steps follows: Randomiser. This block performs the energy dispersal and transport multiplex adaptation using the DVB randomisation polynomial 1+x14+x15 and also by inverting every eighth sync byte.
Reed-Solomon Encoder. This block generates Reed Solomon packets based on the DVB RS(204, 188) code with code generator polynomial:
g(x) = (x+λ0) (x+λ1) (x+λ2)… (x+λ15)
Where λ = 0x02, and field generator polynomial:
p(x) = x8 + x4 + x3 + x2 + 1
Outer Interleaver. This block performs the DVB outer interleaving function with depth I=12 as specified by the DVB standard.
Convolutional Encoder. This block performs the convolutional encoding as specified by DVB.
Interleaver. DVB-T specifies a block based bit interleaver concatenated with a symbol interleaver in a two-step process. If a hierarchical system is selected then the two streams are merged at this point using a modified interleaving equation. The DVB-T(H) extension core provides in-depth interleaving as required..
QAM Mapper. This block performs the QAM constellation mapping using the mapping schemes specified by DVB for QPSK, QAM16 or QAM64. It outputs I/Q QAM symbols to the IFFT core.
Framer. The DVB-T specification details a frame and super-frame structure with scattered, continuous and TPS pilots inserted at various carriers within each symbol. This block manages the pilot insertion dependent on the selected mode (2k, 4k or 8k), and symbol position within a frame. Note that the full system can be switched via software register (or hardware port) to use 2k, 4k or 8k mode. Alternatively a reduced memory 2k only mode may be synthesised.
In-band equalisation An optional in-band equalizer circuit may be specified as a synthesis option. This allows the designer to easily compensate minor phase and gain slope associated with linear filter components on the board.
IFFT. This block performs the Inverse Fast Fourier Transform (IFFT) on the 2k, 4k or 8k carriers. A proprietary architecture is used which yields low Guassian noise, high MER outputs yet utilises low datapath widths. The IFFT also manages the on-air timing of the OFDM symbols by guard interval insertion. An optional windowing function is also included to reduce spurious emissions caused by the OFDM symbol transitions. A further optional non-linear pre-distortion can also be performed.
Resampler. This block resamples the 9·14MHz complex samples output from the IFFT into complex samples at the core clock frequency. This provides an ultra-flexible clocking strategy. This block also scales automatically as required to satisfy the selected channel bandwidth.
Baseband-to-IF. This block provides the option to mix the signal up to a higher IF as defined by a software register. This block may be removed using synthesis options if it is not required.
DAC Aperture Correction. This optional processing step provides compensation for the sin(x)/x (or SINC) distortion that is introduced in the DAC. This block may be removed using synthesis options is the feature is not required
Radio Interface. This block performs some final, register-selectable processing functions to optimise the output for the radio in the target application. For example, the data can be formatted to work with either twos-complement or offset-binary DAC devices. In addition the data is formatted to suit the external vice that could take separate I/Q, multiplexed I/Q or a single IF output.
Additional modes are added to support the Analog Devices AD9857 device that provide up-conversion, SINC filtering and DAC functions in a single package. The AD9857 device requires that the I/Q data be multiplexed onto a single data bus. The ad9857_pdclk input is provided to enable this feature and should be sourced from the AD9857 PDCLK output.
Register Bank. The register bank provides a simple 32-bit interface for reading and writing registers within the modulator block. Full details of the registers within the modulator core are contained within the full data sheet.
