UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
Overview
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
Technical Specifications
Foundry, Node
UMC 55nm
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
- UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
- SMIC 0.13um 90% shrunk HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.13um HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k