UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
Overview
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
Technical Specifications
Foundry, Node
UMC 55nm
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
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- UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
- UMC 55nm ULP/LowK Process via1 ROM compiler well bias
- UMC 55nm ULP/LowK Process via ROM compiler for well bias
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k