Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k

Overview

Single Port SRAM compiler - TSMC 55 nm LP - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k

REACH THE HIGHEST DENSITY
Thanks to smart periphery design
Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
Using Pushed Rules Foundry bitcell
EXTEND BATTERY LIFE
Designed with partitioned array to reach ultra low power consumption at 1.2 V +/-10%
Support a couple of power saving modes: stand by and extinction mode
MAKE INTEGRATION EASIER
MUX option enabling several performance tradeoffs and form factor
Data range flexibility allows easy addition of bits for ECC purposes
Address range flexibility allows easy addition of single rows for redundancy purposes
Embedded extinction switchs ES
The memory can be place in Deep Nwell for noise sensitive applications
ENABLE RIGHT ON FIRST PASS DESIGN
Complete mismatch validation of the memory architecture taking in account local and global dispersion
Extended validation for high coverage rate of the compiler
DECREASE TIME TO MARKET
Multi foundries support using the same architecture

Maturity

In_Production

TSMC

In Production: 55nm LP