UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
Overview
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
Technical Specifications
Foundry, Node
UMC 55nm
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
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- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- UMC 55nm ULP/LowK Process via1 ROM compiler well bias