The PLBv46 to PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI) bus.
The PCI32 core provides an interface with the PCI bus. Details of the LogiCORE™ IP PCI32 core operation is found in the Xilinx LogiCORE IP PCI32 Interface v3, in the Xilinx LogiCORE PCI32 Interface v4 Product Specification, and in the Xilinx LogiCORE IP PCI v3.0 and v4.1 User Guides.
Host bridge functionality (often called North bridge functionality) is an optional functionality. Configuration Read and Write PCI commands can be performed from the PLB-side of the bridge. The PLBV46 PCI Bridge supports a 32-bit/33 MHz PCI bus only.
The PLBV46 PCI Bridge design has parameters that allow customers to configure the bridge to suit their application. The parameterizable features and exceptions to the support of PCI commands are discussed in the data sheet.
Available to all licensees of the PCI32 LogiCORE IP cores.
PLBv46 to PCI Full Bridge
Overview
Key Features
- Independent SPLB, MPLB and PCI clocks
- 33 MHz, 32-bit PCI bus support
- Utilizes two pairs of FIFOs to exploit the separate master and slave PLBV46 IPIF modules.
- Includes a master IP module for remote PCI initiator transactions.
- Includes a slave IP module for remote PLB master transactions.
- The PLBV46 IPIF slave attachment has a timer that limits the time for both read and write data phase operations to complete. When the timer expires, Sl_MErr signal is asserted. See the PLBV46 IPIF Product Specification for details.
- Full bridge functionality
- PLB Master read and write of a remote PCI target (both single and burst)
- PCI Initiator read and write to a remote PLB slave (both single and multiple)
- I/O read and I/O write commands are supported only for PLB master read and writes of PCI I/O space as designated by its associated memory designator parameter. All memory space on the PLB-side is designated as memory space in the PCI sense, therefore, I/O commands cannot be used to access memory on the PLB-side.
- Configuration read and writes are supported.
- PCI Memory Read Line (MRL) command is supported.
- PCI Memory Write Invalidate (MWI) command is supported.
- Supports up to 3 PCI devices (or BARs in PCI context) with unique memory PCI memory space
- Asynchronous FIFOs with burst transfer support and backup capability for retrying transfers as needed.
- PCI Monitor output port to monitor PCI bus activity