Vendor: Eureka Technology, Inc. Category: Protocol Bridge

32-bit PCI Host Bridge

32-bit PCI Host Bridge

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Key features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Designed for ASIC and PLD implementations.
  • Fully static design with edge triggered flip-flops.
  • Efficient back-end interface for different types of user devices.
  • Host bridge design includes bus master, bus target and central system functions.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Combined bus master and target functions.
    • Master function
      • Initiate PCI memory and IO read/write.
      • Automatic transfer restart on target retry and disconnect
    • Target function
      • Memory or IO read/write
      • Configuration read/write
      • Support for back-end initiated target retry, disconnect and abort.
  • Supports Zero wait state and user inserted wait state burst data transfer.
  • Dual write buffer supports write data posting.
  • User controlled burst and non-burst data transfer.
  • Automatic handling of configuration register read/write access.
  • Supports user initiated target retry, disconnect, abort and delayed transaction.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Supports high speed bus request and bus parking.
  • Differentiating Features
    • Backend interface bus type and width selection.
    • Bus arbiter with priority selection.
    • Multiple base address registers.
    • Asynchronous clock domain.
    • Address/Data multiplexing.
    • Backend FIFO interface.
    • Unidirectional host bridge.
    • Burst length and target burst.

Block Diagram

EP430 block diagram

Specifications

Identity

Part Number
EP430
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Eureka Technology, Inc.
HQ: USA
Eureka Technology Inc. provides reusable IP cores for ASIC, PLD and system designs. These system level function cores are designed to:
  • Shorten Time-to-market
  • Eliminate Design Risks
  • Reduce Development Costs
As today's technologies evolve in a very fast pace, design engineers are constantly looking for ways to speed up the design cycle in order to have product in the market ahead of the competitions. The use of reusable IP cores in IC and system design has emerged as the methodology of choice to address the needs for rapid productization, fast prototyping and software/hardware co-development. Eureka Technology help design engineers stay in the forefront of this new design methodology by providing reusable IP cores. Our reusable IP cores are silicon proven and pre-verified to meet and exceed customer requirements. Design risk is virtually eliminated since each one of these cores has been fully tested and proven in real world applications. Since founded in 1993, Eureka Technology has established itself as a leading reusable IP core provider with customer base in the United States, Japan, and Europe. We have provided reusable IP cores to many market leaders in the computer, electronics and semiconductor industries. Our technologies have been incorporated into tens of million dollars' worth of products sold by our customers. We also have entered partnership agreements with leading silicon vendors to incorporate our reusable IP cores into their silicon products. However, our important partnership is the one with our customers and we would like to be the design partner for your next project.
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Frequently asked questions about Protocol Bridge IP cores

What is 32-bit PCI Host Bridge?

32-bit PCI Host Bridge is a Protocol Bridge IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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