AMBA AHB to PCI Host Bridge
Key Features
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Supports AHB bus protocol.
- Downstream access transfer from AHB bus to PCI bus.
- Upstream access transfer from PCI bus to AHB bus.
- AHB bus and PCI bus operate at independent clock domains.
- Total of six write buffers for write data posting for all interfaces.
- Read access to PCI bus handled as delay read to prevent system deadlock.
- Supports AHB burst transfers up to 16 data.
- Supports all AHB slave response types when functioning as AHB bus master.
- PCI interface includes bus master, bus target and configuration access initiation.
- Generates standard PCI type 0 and type 1 configuration accesses.
- Supports early burst termination and CPU master busy.
- Automatic handling of configuration register read/write access.
- Supports target retry, disconnect, abort and wait state insertion.
- Parity generation and parity error detection.
- Includes all PCI specific configuration registers.
- Supports high speed bus request and bus parking.
- Optional PCI bus arbiter with fix, rotating, and custom priority.
- Optimized for ASIC and PLD implementations, including Excalibur PLD.
Block Diagram
Technical Specifications
Short description
AMBA AHB to PCI Host Bridge
Vendor
Vendor Name
Availability
now