MIPI D-PHY Rx ONLY v1.1 @1.5ghz Ultra Low Power & Low Area for IoT & Wearables

Overview

The 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. The D-PHY IP is available on both TSMC’s industry-leading 22nm ultra-low power (22ULP) and 22nm ultra-low leakage (22ULL) process technologies. TSMC 22nm ultra-low power (22ULP) is an ideal foundry technology for applications including image processing, digital TVs, set-top boxes, smartphones and consumer products in terms of its power, performance and area (PPA) optimization, while its 22nm ultra-low leakage (22ULL) technology provides significant power reduction to support IoT and wearable device applications, where power is of paramount importance. MIPI D’Phy as a physical serial communicating layer is gaining traction in the today’s power hungry mobile and mobile related applications due to its low power consumption operation.

The D-PHY IP is also available as a Tx only IP for companies looking to save silicon area and further improve power consumption.


The MIPI D-PHY IP is proven on its own test chip on TSMC 28nm process, which has been licensed by multiple customers since 2016 and validated along with its CSI IP and DSI IP with 3rd Party VIP as a Total IP Solution.

The MIPI D-PHY IP is also available off the shelf on the TSMC 40nm, 28nm, 16nm and 12nm process technologies.

Key Features

  • Compliant with MIPI D-PHY Specification v1.1
    • The MIPI D-PHY uses point-to-point differential interface and has modular architecture supporting multiple data lanes and a clock lane allowing all possible configurations
    • Data lanes support both bidirectional and unidirectional modes, clock lane supports unidirectional communication
    • Supports CSI-2, DSI, and DSI-2
    • One clock lane and up to four data lanes
    • Asynchronous transfer at low-power mode with a bit rate of 10 Mb/s
    • Ultra low-power mode, and high-speed mode for clock lane
    • Ultra low-power mode, high-speed mode, and escape mode for data lane
    • PHY-Protocol Interface (PPI) to connect CSI-2 and DSI applications
    • Supports 80Mbps to 1.5Gbps data rate in high speed mode, 10Mbps data rate in low-power mode
    • Universal Lane configuration can be programmed to address any of the allowed use cases
    • Configurations optimized for a specific use-case are also available
    • Optional resistance termination calibrator
    • Architected to mate perfectly with our high performance PLLs specifically designed to address MIPI applications
    • Support for full-speed internal loopback testability with minimal area overhead for high-volume manufacturing tests in the D-PHY Universal, TX+, and RX+ configurations
    • Support for new Alternate LP Mode, suitable for IoT applications with long channels, enabling Fast Bus Turnaround

Benefits

  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Process & Foundry
    • Available in various foundry processes
    • No external (off-chip) components required
    • Can be ported to other processes
  • Silicon proven
  • Extensive Quality Methodology

Applications

  • For applications including image processing, digital TVs, set-top boxes, smartphones , IoT and wearable device and consumer products in terms of its ultra low power

Deliverables

  • GDS-II Database
  • LVS Netlist
  • Physical Abstract Models (LEF)
  • Timing Models (LIB)
  • Process Specific Integration Guide

Technical Specifications

Foundry, Node
TSMC 40nm, 28nm, 22nm,16nm and 12nm process
Maturity
Silicon Proven
Availability
Now
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Semiconductor IP