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MIPI D-PHY IP

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Search (397)
Compare 397 MIPI D-PHY IP from 23 vendors (1 - 10)
  • MIPI DPHY Verification IP
    • Full MIPI DPHY Transmitter and Receiver functionality.
    • Supports 3.0 MIPI DPHY Specifications.
    • Supports both serial and PPI functionality testing.
    • Supports short and long packets
    Block Diagram -- MIPI DPHY Verification IP
  • MIPI D-PHY Verification IP
    • Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
    • Support HS-IDLE State between two data burst.
    • Support for Alternate calibration Sequence & Preamble sequence.
    • Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
    Block Diagram -- MIPI D-PHY Verification IP
  • LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
    • The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
  • MIPI D-PHY Verification IP
    • Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
    • Support HS-IDLE State between two data burst.
    • Support for Alternate calibration Sequence & Preamble sequence.
    • Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
    Block Diagram -- MIPI D-PHY Verification IP
  • MIPI D-PHY
    • Multiple Configurations Possible. TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
    • Complete Function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
    • Integrated BIST Capable of producing and checking PRBS, CRPAT, and CJTPAT
    Block Diagram -- MIPI D-PHY
  • MIPI D-PHY Universal IP in UMC 28HPC+
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    • Embedded, high performance, and highly programmable PLL
    • Supports both low-power mode and high speed mode with integrated SERDES
    Block Diagram -- MIPI D-PHY Universal IP in UMC 28HPC+
  • MIPI D-PHY IP 4.5Gbps in TSMC N7
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    Block Diagram -- MIPI D-PHY IP 4.5Gbps in TSMC N7
  • MIPI D-PHY TX PHY and DSI controller
    • Scalability and Flexibility: Supports multiple data lanes for higher aggregate bandwidth, any of the multiple lanes can be configured into Clock Lane
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    Block Diagram -- MIPI D-PHY TX PHY and DSI controller
  • MIPI DPHY v1.2 TX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 TX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
  • MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
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