Low Power PLL for TSMC 40nm ULP

Overview

Key Features

• Wide range M, P, and N integer dividers.
• 40MHz – 600MHz output frequency range.
• Input frequency range 1.4MHz – 32MHz.
• 15pS RMS cycle to cycle jitter.
• Lock-detect function.
• Optional bypass function.
• Level shifted IO.
• Well-defined, fast startup behavior.
• -40°C to 125°C temperature operation.
• Small area: 0.03mm2 in 40nm CMOS.
• 100µW typical power dissipation.
• 0.82-1.1V digital and analog supplies.
• Silicon proven.

Block Diagram

Technical Specifications